Versatile Interface Peripheral - VipSticks

Be sure to read the introduction.

Pin Assignments

Addressing Capabilities

The slave peripheral address is output by the master on signals PAD0,PAD1, and PAD2.  All slaves ignore these pins until PSEL is brought high by the master.   These signals are compared with an on board address (e.g., set by a 3 pin dip switch) and if the address matches, the slave connects to the multiplexed IO lines.  

Eight slave addresses are available on the bus (numbered 0-7).

The address match logic is implemented in hardware on each slave.  This is done in hardware to ensure that software bugs do not allow a slave to monopolize the bus during prototyping.  The hardware required is a 3 position DIP switch (about 0.55 US) and a 74HC85 magnitude comparator (about 0.49 US).   3 lines of the dip and the PSEL bit are fed into the comparator.  The equivalence output is fed into the signal connect/disconnect stage.

The PAD0, PAD1, and PAD2 lines are placed on the low order bits of the port so that the master may output them as a number 0 - 7 without further processing (i.e., shifting, etc.).

Shared Signal Connect/Disconnect

The slave is isolated from the SCL, MISO, MOSI, PIRQ lines until the address match is made.  Once the address is matched, these lines are connected bi-directionally to the slave logic.  This ensures that only one slave may be addressed at the same time (if each slave has a unique address as recommended).

The signal connect/disconnect is implemented in hardware on each slave by a 4066 Quad Bilateral switch (about 0.29 US).  The output from the address detection stage is used as the ON signal to the switch.  In this way, only the addressed slave can read or write the MOSI, MISO, clock, and interrupt request lines.

These lines were placed adjacent to the address lines so that all 6 of the lines which are only relevant when PSEL is high would be contiguous.  The intent is to allow other (carefully constrained) peripherals to be driven when PSEL is low.

Note: the hardware used for address detection and signal connection adds about $1.50 US to the cost of the slave peripheral.  It could be argued that this same functionality could be done in software.  And, that would be true.  It would also require a processor on each slave and would be susceptible to software bugs.   Placing these functions in hardware allows for dumb slave peripherals and makes the design more robust and easier to implement.

Address and IO Functionality

The slave peripherals sit idle on the bus until the 4 bit address match is present (PAD0 - PAD2 and  PSEL).  When the address match is made, the SCL, MISO, MOSI, and PIRQ lines are connected to the slave.  As long as the address match is held, the master may use SCL, MISO, MOSI, and PIRQ to communicate with the slave.  This will generally be used to transmit synchronous serial data.  PIRQ is used by the slave to request service from the master (see Slave Interrupt Requests of the Master).

When the PSEL line is low, no VipStick slaves will receive or transmit on these lines.  They may safely be used by the master to communicate with other devices.  PAD0 - PAD2 may also be used.  However, any other peripherals on the bus must be careful to ignore any signals on these lines  when PSEL is high.

Slave Interrupt Requests of the Master

The PEND and PIRQ signals are used to provide the slaves a means to request service of the master on a interrupt basis.  Any slave wishing to interrupt the master should pull down PEND and raise PIRQ.  Note that the PIRQ line will not be connected to the bus unless the slave is addressed by the master.

The master should be configured in software to be interrupted by the PEND signal.  The master then addresses each slave in turn.  If the PIRQ line is high, the addressed slave is requesting service.  A pullup on the PEND line allows multiple slaves to drive the line low simultaneously.

After the slave has been serviced, it should drop both PEND and PIRQ.

After servicing the slave, the master should test PEND and if the line is still low, continue polling the slaves for the next one with PIRQ held high.

Note that if the PIRQ signal is high when PSEL is low, the interrupt is NOT from a VipStick peripheral, but from another type of peripheral.  This allows non-VipSticks to interrupt the master.

Notes on the Design and Why it is the Way it is

This is essentially a design for putting SPI type peripherals on the SimmStick bus.  The SCL, MISO, and MOSI signal names come from SPI nomenclature.  Other serial protocols (I2C, Microwire, Dallas 1-Wire, etc.) can easily be implemented as well.  No communications protocol is specified - only the address match and signal connection functionality.

The design uses the SCL for the clock for serial data transfer.  These lines are also used by the DT101 boards for on-board serial I2C EEPROM communication.  The master and slave should be careful not to generate a valid I2C start bit when communicating on the VipStick bus (do not change the state of SDA while SCL is high).  The SDA line is not used by VipStick peripherals.  

Another thought during design was to put the address lines and latch on the D8 - D11 signals. That would free up 4 lines on port B, but would require extra hardware on the DT101 to multiplex the lines. I am still toying with that idea. But, again, I wanted to use unmodified DT101's if possible. And unmodified motherboards as well. So, I stayed away from the pins used for RS-232, serial data, and real time clock. 

The way I freed up pins on port B was to specify that the address lines, MISO, MOSI, and PIRQ, (that's 6 pins) can be used for other purposes as long as the PSEL address latch line is "off". If you need those 6 pins, design your hardware so that it was disabled when PSEL is "ON". I even tried to consider the impact on the DT205, but notice that you can put the relay signals on D8 - 15 if necessary.

I considered a new processor board design which would put all of the lines on D8 - D15 through multiplexing hardware, but I wanted to stay in the spirit of the contest which says we should incorporate a DT101, etc. For a long time, the design even included a multi-mastering capability which allowed multiple processors to arbitrate the bus and peripherals. I gave that up as more complex than 99% the real world was going to need (but what fun that would have been - multi-processor SimmSticks, yea).

Notes on Specific Pin Assignments

The pin assignments were given a great deal of thought.  Initially, the address lines were placed on the low order bits to make the code for putting an address on to the bus as simple as possible.  This was changed in order to facilitate better interrupt handling by the master and slaves.

RB0/INT is used for the PEND signal so that a slave can directly interrupt the master to request attention. 

For similar reasons, the Address lines are placed on pins RB4 - RB7.  This allows an "Interrupt on change" to be processed by the slaves or non-VipStick if desired.

PSEL was placed on pin RB7 so that the lines which can be used by other devices while PSEL is low would be adjacent to each other.

Schematic

The basic Vipstick logic consists of the Dip switch to set the board address, the 74LS85 to handle the address match, and the 4066 bi-directional switch.